The present invention relates to semiconductor devices, and more particularly to sub-0.05 xcexcm fully-depleted silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) devices having a relatively low source and drain resistance and minimal overlap capacitance. The present invention also relates to various methods of fabricating such fully-depleted SOI MOSFET devices.
Over the past twenty-five years or so, the primary challenge of very large scale integration (VLSI) has been the integration of an ever-increasing number of metal oxide semiconductor field effect transistor (MOSFET) devices with high yield and reliability. This was achieved mainly in the prior art by scaling down the MOSFET channel length without excessive short-channel effects. As is known to those skilled in the art, short-channel effects are the decrease of threshold voltage V, in short-channel devices due to two-dimensional electrostatic charge sharing between the gate and the source/drain diffusion regions.
In recent years, and as channel lengths are being scaled below 0.1 xcexcm, SOI complementary metal oxide semiconductor (CMOS) technology has received considerable interest in VLSI for its potential low-voltage, low-power, and high-speed advantages in comparison to bulk CMOS devices. As known to those skilled in the art, SOI structures include an insulating layer, i.e., buried oxide region (BOX), that electrically isolates a top Si-containing layer from a bottom Si-containing layer. The top Si-containing, i.e., the SOI layer, serves as the area in which electronic devices such as MOSFETs can be fabricated.
Thin film SOI MOSFETs in which the top Si-containing layer has a thickness of about 20 nm or less are of special interest due to improved isolation, reduced parasitic capacitance as well as the reduction of short-channel and floating body effects that can be obtained from such technology. Despite the known advantages with thin film SOI technology, processing challenges exist which substantially hamper the use of thin film SOI MOSFETs in semiconductor integrated circuits. For example, prior art processes for fabricating thin film SOI MOSFETs have difficulty in forming a thin (20 nm or less) SOI channel region, while simultaneously being able to maintain abutting thick SOI source and drain regions. Thick source and drain regions are desirable since they permit the formation of a low sheet resistance silicide layer.
In view of the above-mentioned drawbacks with fabricating prior art thin SOI MOSFETs, there exists a need for providing a new and improved method for fabricating SOI MOSFETs which have a thin SOI device channel region, i.e., a recessed channel, as well as thick SOI source and drain regions abutting the thin channel region.
The present invention provides a technique for the fabrication of sub-0.05 xcexcm channel length fully-depleted SOI MOSFET devices that exhibit excellent short-channel effects, low source and drain resistance and minimal overlap capacitance. The inventive technique utilizes a damascene-gate process which allows self-aligned thinning of a top Si-containing layer (i.e., SOI layer) of an SOI structure in the channel region to minimize short-channel effects while simultaneously maintaining thick SOI source and drain regions to permit formation of a low sheet resistance silicide layer. By utilizing a thin nitride layer deposition technique during the inventive method to form thin inner nitride spacers in the structure, the overlap capacitance between the gate and the source and drain regions is minimized.
Specifically, the method of the present invention which is capable of forming sub-0.05 xcexcm channel length fully-depleted SOI MOSFET devices comprises the steps of:
forming at least one dummy gate region atop an SOI layer, said dummy gate region comprising at least a sacrificial polysilicon region and first nitride spacers located on sidewalls of said sacrificial polysilicon region;
forming an oxide layer that is coplanar with an upper surface of said dummy gate region;
removing said sacrificial polysilicon region to expose a portion of the SOI layer;
forming a thinned device channel region in said exposed portion of the SOI layer;
forming inner nitride spacers on exposed walls of said first nitride spacers;
forming a gate region (including gate dielectric and gate conductor) over said thinned device channel region; and
removing said oxide layer so as to expose thicker portions of said SOI layer than said device channel region.
In one embodiment of the present invention, various implants such as extension implants, halo implants, and source/drain implants are performed after the oxide layer has been removed.
In yet another embodiment of the present invention, the various implants are performed during formation of the dummy gate region.
Following the removal of the oxide layer from the structure which exposes the thick SOI regions abutting the thinned device channel region, the present invention contemplates forming salicide regions in the thick SOI regions; or forming an epi Si layer; or forming an epi layer and thereafter a salicide layer.
Another aspect of the present invention relates to a sub-0.05 xcexcm channel length fully-depleted SOI MOSFET device which is fabricated using the processing steps of the present invention. Specifically, the sub-0.05 xcexcm channel length fully-depleted SOI MOSFET comprises
an SOI layer having a channel region of a first thickness and abutting source/drain regions of a second thickness present therein, wherein said second thickness is greater than said first thickness and said source/drain regions have a salicide layer present thereon; and
at least one gate region present atop said SOI layer.